Software & Systems Engineer
Real-time systems,built from silicon to API.
Software and systems engineer working across embedded and backend. Six months as the sole engineer on a heterogeneous Zynq UltraScale+ / Hailo-8 video platform with no reference implementation — 25 FPS, sub-40ms glass-to-glass. Now building the backend services and infrastructure that sit above it.
About
Silicon on one end, the API on the other.
I'm a software and systems engineer who ended up going deep on both ends of the stack: FPGA fabric and RTL timing on one side, REST APIs and relational data on the other. The common thread is discipline — correctness, memory safety, and validation you can reproduce, not the kind you hope for.
My reference project is a bachelor thesis at HEPIA (HES-SO Geneva): a heterogeneous real-time image-processing platform combining a Zynq UltraScale+ MPSoC with a Hailo-8 NPU. Six months, one engineer, no reference implementation — training and deploying a custom CNN to the edge, building the GStreamer pipeline around it, extending the FPGA fabric with a memory-to-memory video pipeline in Vivado, and building the ARM64 cross-compilation toolchain from scratch because the vendor framework didn't support one.
Since then I've been building and operating backend systems independently — Python/FastAPI services, PostgreSQL/PostGIS data models, the Linux infrastructure they run on — with the same stage-by-stage validation habit I built debugging DMA regressions on embedded Linux.
I learned to program without AI assistance and use AI tools daily now — reviewing generated code section by section and rejecting what's wrong rather than trusting it by default.
Valentin Bernillon
Available for work
$ ./traits --verbose
[01] Independent — comfortable with no reference implementation to follow
[02] Validates incrementally: staged checkpoints, isolated test harnesses, deterministic synthetic input
[03] Documents unfinished work honestly — what succeeded, what didn't, and why
[04] Full-stack ownership mindset: from RTL and firmware to the database query that serves the API
Flagship project
Heterogeneous FPGA–NPU Real-Time Image Processing Platform
Bachelor thesis, HEPIA (HES-SO Geneva) — sole engineer, no reference implementation
Hover a block to trace its data path
Sustained frame rate
Glass-to-glass latency
Hailo-8 NPU compute @ ~2.5W
Solo, no reference implementation
Context
A real-time, multi-camera image-processing platform combining an AMD Zynq UltraScale+ MPSoC (ZCU104, XCZU7EV-2) with a Hailo-8 NPU (up to 26 TOPS at ~2.5W, PCIe Gen2 x1) and four Raspberry Pi Camera Module 2 sensors. Built on top of an open-source reference platform, extended and hardened over six months under supervisor Laurent Gantel.
What I actually built
Designed, trained and exported a custom 6-class CNN (TensorFlow/Keras, ~3.3M parameters) and deployed it end to end through the Hailo Dataflow Compiler — ONNX → HAR → 8-bit quantisation → HEF.
Built the full real-time GStreamer pipeline: capture → colour-space conversion & resize → Hailo-8 inference (synchailonet) → post-processing → overlay → display, holding 25 FPS at sub-40ms latency on a single camera stream.
Wrote a custom C++ post-processing module compiled as an ARM64 shared object: tensor dequantisation via the HailoRT API, argmax classification, configurable confidence thresholding, and a degraded-mode fallback path.
Built an ARM64 cross-compilation toolchain from scratch after finding the vendor framework had no cross-compilation support: PetaLinux SDK build, an isolated CMake sysroot, and pkg-config integration for the HailoRT runtime.
Extended the FPGA design in Vivado with a modular, memory-to-memory video pipeline (AXI VDMA, Video Processing Subsystem, AXI-Stream) — insertable without full re-synthesis and meeting timing closure at 250 MHz.
Diagnosed a DMA-transfer regression and a failing vendor Mem2Mem V4L2 framework down to root cause — deprecated, incompatible with current PetaLinux releases — by rebuilding the pipeline stage by stage with validated checkpoints and deterministic synthetic-input test harnesses, before evaluating three alternative approaches.
Process
Model, from scratch
A generic pre-trained model would have skipped the part worth learning. Trained a 6-class CNN in TensorFlow/Keras on ~12,240 images (128×128 RGB), exported to ONNX opset 13, deliberately kept simple to validate the full pipeline rather than chase benchmark accuracy.
Compile for silicon
ONNX has no idea an NPU exists. Parsed to HAR, quantised to 8-bit against a calibration set, and compiled to Hailo's executable format (HEF) across 8 compute clusters — with the resourcing trade-offs of a reduced calibration set made explicit rather than hidden.
Wire it into real time
Six-stage GStreamer pipeline built incrementally — baseline capture, tee/funnel splitting, colour conversion, inference, post-processing, overlay — each stage validated in isolation before the next was added.
Push into the fabric
Where the CPU pipeline hit a wall — four simultaneous 1080p streams crashing the ARM cores — the fix moved into programmable logic: a modular AXI VDMA memory-to-memory pipeline in Vivado, synthesised and timing-closed at 250 MHz.
What didn't make it — honestly
Six months, one engineer, no reference implementation. Some things didn't get finished — here's exactly what and why.
- 01
Multi-camera stability: the software pipeline is stable on a single stream but the ARM cores crash under four simultaneous streams — the honest limitation, not glossed over.
- 02
FPGA video pipeline: RTL synthesised and timing-closed at 250 MHz, but Device Tree / V4L2 exposure of the new pipeline stage was not finished within the project timeline.
- 03
NPU-native preprocessing: an exploratory Hailo .alls script to move colour conversion and resize onto the NPU itself was promising but abandoned unfinished — feasibility confirmed, implementation incomplete.
Path
Experience & education
2017 — 2026
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Experience
Education
Hover or click a milestone above to see its details.
Other work
Hardware, software, and the systems around them.
Beyond the thesis: PCB design, backend platforms, kernel programming, and the occasional game built for a practical exam.
Toolbox
From RTL to REST — the full range.
Eight domains, one engineer. What's used together in practice, not a list padded for keywords.
Embedded & FPGA
- FPGA / RTL design (Xilinx Vivado)
- Timing closure & synthesis
- AXI VDMA / Video Processing Subsystem
- Embedded Linux (PetaLinux)
- Device Tree & U-Boot
- ARM64 cross-compilation toolchains
- CMake
Microcontrollers & RTOS
- C / C++
- FreeRTOS
- Real-time systems & multitasking
- Interrupt handling & memory management
- SPI, I²C, CAN, UART, PCIe, BLE GATT, LoRa
- Oscilloscopes, logic & protocol analyzers
Edge AI & Multimedia
- Hailo-8 NPU / HailoRT
- ONNX / model quantisation
- TensorFlow / Keras
- GStreamer pipeline design
- CNN deployment on constrained hardware
Backend & Data
- Python
- FastAPI
- REST API design
- PostgreSQL / PostGIS
- SQL & schema design
- Data ingestion & ETL pipelines
- Pydantic v2
- HTMX / Alpine.js
Infrastructure & DevOps
- Docker / docker-compose
- Linux server administration
- Proxmox / KVM
- WireGuard & Tailscale VPN
- Reverse proxy, firewalls (nftables)
- CI/CD, Git/GitHub
- Routing, switching & network segmentation (CCNA)
Hardware & PCB
- Altium Designer
- Schematic & PCB layout
- SMD assembly (pick-and-place, reflow)
- Bring-up & multimeter validation
Mobile & Frontend
- Flutter / Dart
- JavaScript
- HTML / CSS
- REST API integration
AI-Assisted Engineering
- AI-assisted development (Claude Code, section-by-section review)
- LLM integration & prompt design
- n8n workflow automation
- Structured output validation
Tools & technologies
Contact
--:-- local (Colombia)Let's talk about what you're building.
Open to embedded systems, edge-AI and backend/infrastructure roles. Available for full-time roles, 100% remote.
© 2026 Valentin Bernillon. Bogotá, Colombia — Swiss citizen, remote.
Designed & built with Next.js, React Three Fiber and GSAP.