Software & Systems Engineer
Real-time systems,built from silicon to API.
I'm Valentin Bernillon, a Software & Embedded Systems Engineer. Trained at HEPIA (HES-SO Geneva), I've worked across the full stack — from FPGA timing and embedded Linux to backend services and databases — and I pick whichever end actually solves the problem. Today, I design and operate backend platforms independently, from data model to deployment.
About
Silicon on one end, the API on the other.
I think about software the way I first learned to think about hardware: nothing is trusted until it's been proven at every layer. My training is in embedded systems, in Geneva — FPGA fabric, RTL timing, kernel-level code — and that habit followed me into backend engineering. I'm just as comfortable at silicon as I am at the API surface, and I usually end up owning the whole path between the two.
My approach is diagnostic, not trial-and-error: trace a failure to its actual cause before touching anything, and only move forward once the current stage is actually proven. That habit came from debugging a hardware-software boundary with nothing to fall back on — no vendor documentation that held up, no prior engineer's notes to check against — and it's shaped every project since, including the write-ups on this site, where the unfinished parts are listed as plainly as the finished ones.
That project-ownership habit is how I still work: alone, across the whole stack, backend to infrastructure. I use AI tools daily now, after learning to program without them — I review what they generate the same way I'd review anyone else's code, and I validate against real behavior rather than trusting a simulated test.
Outside the stack, I spent two years tutoring computer science and math — explaining something clearly enough for someone else to rebuild the reasoning is its own kind of debugging. I work daily in French, English, and Spanish — the Spanish picked up through immersion, not a classroom — and picked up a PADI Divemaster certification along the way: same instinct as everything else, learn it properly or not at all.
Valentin Bernillon
Available for work
$ ./traits --verbose
[01] Independent — comfortable with no reference implementation to follow
[02] Validates incrementally: staged checkpoints, isolated test harnesses, deterministic synthetic input
[03] Documents unfinished work honestly — what succeeded, what didn't, and why
[04] Full-stack ownership mindset: from RTL and firmware to the database query that serves the API
Flagship project
Heterogeneous FPGA–NPU Real-Time Image Processing Platform
Bachelor thesis, HEPIA (HES-SO Geneva), Feb–Sep 2025 — sole engineer, no reference implementation
Hover a block to trace its data path
Sustained frame rate
Glass-to-glass latency
Hailo-8 NPU compute @ ~2.5W
Solo, no reference implementation
Context
A real-time, multi-camera image-processing platform combining an AMD Zynq UltraScale+ MPSoC (ZCU104, XCZU7EV-2) with a Hailo-8 NPU (up to 26 TOPS at ~2.5W, PCIe Gen2 x1) and four Raspberry Pi Camera Module 2 sensors. No finished system like this existed to copy: I started from an open-source proof-of-concept ("Multi-camera YOLOv5 on Zynq UltraScale+ with Hailo-8"), picked after a technology survey as the most solid available base, then extended and hardened it over seven months (February–September 2025) under supervisor Laurent Gantel.
What I actually built
Designed, trained and exported a custom CNN (TensorFlow/Keras, ~3.3M parameters) that classifies how many fingers are held up on a single hand — a deliberately simple 6-class task chosen to validate the deployment pipeline, not to chase accuracy — and deployed it end to end through the Hailo Dataflow Compiler: ONNX → HAR → 8-bit quantisation → HEF.
Built the full real-time GStreamer pipeline: capture → colour-space conversion & resize → Hailo-8 inference (synchailonet) → post-processing → overlay → display, holding 25 FPS at sub-40ms latency on a single camera stream.
Wrote a custom C++ post-processing module compiled as an ARM64 shared object: tensor dequantisation via the HailoRT API, argmax classification, configurable confidence thresholding, and a degraded-mode fallback path.
Built an ARM64 cross-compilation toolchain from scratch after finding the vendor framework had no cross-compilation support: PetaLinux SDK build, an isolated CMake sysroot, and pkg-config integration for the HailoRT runtime.
Extended the FPGA design in Vivado with a modular, memory-to-memory video pipeline (AXI VDMA, Video Processing Subsystem, AXI-Stream) — insertable without full re-synthesis. Compared two hardware variants on measured LUT/BRAM overhead (Framebuffer Read/Write vs. AXI VDMA); both met timing closure at 250 MHz, with VDMA chosen for its cleaner fit with standard Xilinx Linux drivers.
Diagnosed a DMA-transfer regression and a failing vendor Mem2Mem V4L2 framework down to root cause — deprecated, incompatible with current PetaLinux releases — by rebuilding the pipeline stage by stage with validated checkpoints and deterministic synthetic-input test harnesses, before evaluating three alternative approaches.
Process
Model, from scratch
A generic pre-trained model would have skipped the part worth learning. Trained a 6-class CNN in TensorFlow/Keras on ~12,240 images (128×128 RGB), exported to ONNX opset 13, deliberately kept simple to validate the full pipeline rather than chase benchmark accuracy. It hit 100% validation accuracy — a sign of an easy, narrow dataset, not a benchmark win.
Compile for silicon
ONNX has no idea an NPU exists. Parsed to HAR, quantised to 8-bit against a calibration set, and compiled to Hailo's executable format (HEF) across 8 compute clusters — with the resourcing trade-offs of a reduced calibration set made explicit rather than hidden.
Wire it into real time
Six-stage GStreamer pipeline built incrementally — baseline capture, tee/funnel splitting, colour conversion, inference, post-processing, overlay — each stage validated in isolation before the next was added.
Push into the fabric
Where the CPU pipeline hit a wall — four simultaneous 1080p streams crashing the ARM cores — the fix moved into programmable logic: a modular AXI VDMA memory-to-memory pipeline in Vivado, synthesised and timing-closed at 250 MHz.
What didn't make it — honestly
Seven months, one engineer, no reference implementation. Some things didn't get finished — here's exactly what and why.
- 01
Multi-camera stability: the software pipeline is stable on a single stream but the ARM cores crash under four simultaneous streams — the honest limitation, not glossed over.
- 02
FPGA video pipeline: RTL synthesised and timing-closed at 250 MHz, but Device Tree / V4L2 exposure of the new pipeline stage was not finished within the project timeline.
- 03
NPU-native preprocessing: an exploratory Hailo .alls script to move colour conversion and resize onto the NPU itself was promising but abandoned unfinished — feasibility confirmed, implementation incomplete.
Path
Experience & education
2018 — 2026
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Experience
Education
Hover or click a milestone above to see its details.
Other work
Hardware, software, and the systems around them.
Beyond the thesis: PCB design, backend platforms, kernel programming, and the occasional game built for a practical exam.
Toolbox
From RTL to REST — the full range.
Eight domains, one engineer. What's used together in practice, not a list padded for keywords.
Embedded & FPGA
- FPGA / RTL design (Xilinx Vivado)
- Timing closure & synthesis
- AXI VDMA / Video Processing Subsystem
- Embedded Linux (PetaLinux)
- Device Tree & U-Boot
- ARM64 cross-compilation toolchains
- CMake
Microcontrollers & RTOS
- C / C++
- FreeRTOS
- Real-time systems & multitasking
- Interrupt handling & memory management
- SPI, I²C, CAN, UART, PCIe, BLE GATT, LoRa
- Oscilloscopes, logic & protocol analyzers
Edge AI & Multimedia
- Hailo-8 NPU / HailoRT
- ONNX / model quantisation
- TensorFlow / Keras
- GStreamer pipeline design
- CNN deployment on constrained hardware
Backend & Data
- Python
- FastAPI
- REST API design
- PostgreSQL / PostGIS
- SQL & schema design
- Data ingestion & ETL pipelines
- Pydantic v2
- HTMX / Alpine.js
Infrastructure & DevOps
- Docker / docker-compose
- Linux server administration
- Proxmox / KVM
- WireGuard & Tailscale VPN
- Reverse proxy, firewalls (nftables)
- CI/CD, Git/GitHub
- Routing, switching & network segmentation (CCNA)
Hardware & PCB
- Altium Designer
- Schematic & PCB layout
- SMD assembly (pick-and-place, reflow)
- Bring-up & multimeter validation
Mobile & Frontend
- Flutter / Dart
- JavaScript
- HTML / CSS
- REST API integration
AI-Assisted Engineering
- AI-assisted development (Claude Code, section-by-section review)
- LLM integration & prompt design
- n8n workflow automation
- Structured output validation
Tools & technologies
Contact
--:-- local (Colombia)Let's talk about what you're building.
Open to embedded systems, edge-AI and backend/infrastructure roles. Available for full-time roles, 100% remote.
© 2026 Valentin Bernillon. Bogotá, Colombia — Swiss citizen, remote.
Designed & built with Next.js, React Three Fiber and GSAP.